Two-Step Single-Slope ADC Utilizing Differential Ramps for CMOS Image Sensors

Abstract

This paper presents a two-step single-slope (TS-SS) analog-to-digital converter (ADC) for CMOS image sensors (CIS). The proposed TS-SS ADC divides the pixel signal into small and large signal regions using a precomparator. When quantizing large pixel signals, the TS-SS ADC enters accelerated mode, which leverages the differential topology of the ramp generator to speed up quantization. The accelerated mode reduces the row cycle, resulting in a 31.3% reduction at 320 MHz clock from 27.3 to 18.75 µs. The designed 12-bit TS-SS ADC was designed in a 110 nm 1P4M CMOS technology, and its linearity was verified by process corner post-simulation and Monte Carlo simulation.

1 Introduction

Nowadays, CMOS image sensors (CIS) have been extensively utilized in various electronic devices, including smartphones, digital cameras and security equipment. The demand for high-quality imaging has been steadily rising across all sectors where CISs are employed. Consequently, achieving higher pixel resolution and faster frame rates has become a crucial challenge that needs to be addressed.

Single-slope (SS) analog-to-digital converters (ADCs) are widely used in commercial large-size and high-resolution CIS products due to their advantages of low power consumption and small footprint. However, a drawback of SS ADCs is that N-bit resolution requires 2${^N}$ conversion clocks, resulting in a long row cycle, This limitation hinders their application in large array and high-frame-rate CIS systems. N represents the number of bits in the ADC.

The two-step (TS)-based SS ADC approach has been extensively studied in previous research to enhance the speed of SS ADCs. In Refs. [8, 9, 12, 14, 16], the quantization process involves two steps: coarse quantization followed by fine quantization. Initially, the quantization range $\textit{V}{_\textrm{range}}$ is determined, and the input signal’s range is divided based on the coarse quantization ($\textit{V}{_\textrm{range}}$ / 2${^C}$ per segment signal). Subsequently, fine quantization ($\textit{V}{_\textrm{range}}$ / 2${^{C+F}}$ per segment signal) is performed based on the coarse quantization results. For an N-bit resolution TS-SS ADC, this approach requires only 2${^C}$ + 2${^F}$ conversion clocks (N = C + F), C and F represent the number of coarse and fine bits, respectively. However, switching between coarse and fine quantization may introduce non-negligible linearity errors and the overall performance of the SS ADC will be affected. In Ref. [14], multiple ramp generators are used, with each ramp covering a portion of the ADC input swing. However, multiple ramps increase more circuit area and analog power consumption, and the linearity of multiple ramps is more difficult to match. In addition, SS ADCs can be combined with SAR algorithms and cyclic algorithms, i.e., hybrid ADCs, which can also significantly decrease the row cycle of SS ADCs [1, 3, 6, 10, 15]. For example, the SAR ADC algorithm is used to quantize the upper six bits and the SS ADC algorithm is used to quantize the lower six bits [6]. However, hybrid ADCs are vulnerable to the step size of the ramp signal and the gain error of the capacitor DAC. The row cycle of the SS ADC also can be cut in half by determining the 1 most significant bit (MSB) over the full ADC reference range, as demonstrated in Refs. [5, 13]. These approaches demonstrate the ongoing efforts to enhance the speed and performance of SS ADCs through innovative techniques and combinations of existing algorithms.

However neither method provides a detailed discussion of the effects of parasitic capacitance. In this paper, we propose a new TS-SS ADC structure, which divides the pixel signal into large and small signal regions by a precomparison. The problem of increased counter power consumption can be solved by reducing the number of bits in the ADC when quantizing large signal [2]. The benefit of the proposed TS-SS ADC is that it does not have any effect on the pixel signals in the small signal region and accelerates only for the quantization of the pixel signals in the large signal region. Furthermore, by adjusting the programmable capacitor array and the clock frequency in the accelerated mode, the deviation in linearity between the two modes can be minimized to a level much smaller than the effect caused by shot noise. This indicates that the proposed TS-SS ADC approach effectively manages linearity while addressing the impact of parasitic capacitance.

This paper is organized as follows. Section 2 describes the working principle and circuit implementation of the proposed structure. Simulation results and comparisons with various column-parallel SS ADC are presented in Sect. 3. Finally, Sect. 4 concludes this paper.

2 Principle of the Proposed Technique

2.1 Conventional SS ADC

As shown in Fig. 1 , the conventional column-parallel SS ADC is composed of comparators, counters and a ramp generator. The ramp generator generates a reference signal $\textit{V}{_\textrm{ramp}}$, which is compared with the pixel signal $\textit{V}{_\textrm{pixel}}$ of each column. This comparison process is controlled by digital timing. Once the comparison is completed, the ADCs asynchronously store the counting results corresponding to the pixel signals.

Fig. 1

Simplified schematic of a conventional SS ADC

Fig. 2

Timing diagram of conventional SS ADC with DCDS

Figure 2 shows the timing diagram of the conventional column-parallel SS ADC with digital correlated double sampling (DCDS) [4, 7]. The process begins with resetting the comparator, after which the ramp signal $\textit{V}{_\textrm{ramp}}$ is compared with the signal $\textit{V}{_\textrm{rst}}$. The resulting quantization result $\textit{D}{_\textrm{out1}}$ represents the quantized value for $\textit{V}{_\textrm{rst}}$. Next, the pixel signal $\textit{V}{_\textrm{sig}}$ ($\textit{V}{_\textrm{sig}}$ = $\textit{V}{_\textrm{rst}}$ - $\Delta$ $\textit{V}{_\textrm{pixel}}$) is sampled, and the ramp signal $\textit{V}{_\textrm{ramp}}$ is compared with $\textit{V}{_\textrm{sig}}$. The resulting quantization result $\textit{D}{_\textrm{out2}}$ represents the quantized value for $\textit{V}{_\textrm{sig}}$. Signal Comp_out represents the output of the comparator. The time delay of $\textit{t}{_\textrm{d}}$ of signal Comp_out, is caused by non-ideal effects such as the offset ($\textit{V}{_\textrm{offset}}$) and response delay ($\textit{t}{_\textrm{delay}}$) of the comparator. According to the operation of subtracting the quantized code values in the signal and reset phases, the quantization result of the pixel signal $\Delta$ $\textit{V}{_\textrm{pixel}}$ can be obtained as $\textit{D}{_\textrm{out}}$ = $\textit{D}{_\textrm{out2}}$ - $\textit{D}{_\textrm{out1}}$. The subtraction can be achieved through a bidirectional counter or a bitwise inverter (BWI). BWI inverts each bit of the binary output $\textit{D}{_\textrm{out1}}$ to get the inverse value and adds 1 to get the complement value (2${^N}$- $\textit{D}{_\textrm{out1}}$). In the signal phase, the counter starts counting from the complement value (2${^N}$- $\textit{D}{_\textrm{out1}}$) to get the final count result ($\textit{D}{_\textrm{out2}}$ + (2${^N}- \textit{D}{_\textrm{out1}}$)). 2${^N}$ will not be credited to the final output, so the actual output is $\textit{D}{_\textrm{out2}}$ - $\textit{D}{_\textrm{out1}}$. This DCDS operation effectively eliminates the effects of comparator mismatch and delay by extracting the difference between two quantized values.

2.2 Proposed TS-SS ADC

While retaining the DCDS functionality, we propose a new TS-SS ADC conversion scheme that utilizes the differential topology characteristic of the ramp generator for acceleration. As shown in Fig. 3a, the ramp generator in this design utilizes a current steering digital-to-analog converter (DAC). In order to make a trade-off among the circuits area, DNL and INL, the hybrid-code DAC is chosen for our design: the binary-code DAC is used for the lower 5 bits and the thermometer-code DAC is used for the upper 6 bits [11]. The cascaded sub-current source with high output impedance is used to better isolate the effects of switching variations. In switching circuit, two PMOS transistors in series are used to isolate the effects of the switching transistor directly on the output node. $\textit{V}{_\mathrm{switch\_n}}$ and $\textit{V}{_\mathrm{switch\_p}}$ are two low-level crossover inverted clocks that generated by a current-source latching circuit.

During the signal phase, the required ramp signal clock step is (($\textit{V}{_\textrm{peak}}$ / $\textit{V}{_\textrm{range}}$) $\times$ 2${^N}$) for a conventional SS ADC. And the required ramp signal clock step is (($\textit{V}{_\textrm{peak}}$ / $\textit{V}{_\textrm{range}}$) $\times$ 2${^{N-1}}$) for this proposed TS-SS ADC, the time required when the $\textit{V}{_\textrm{RF}}$ is a constant voltage is ignored. Therefore, the entire row cycle can be reduced by (($\textit{V}{_\textrm{peak}}$ / $\textit{V}{_\textrm{range}}$) $\times$ 2${^{N-1}}$) clock steps, as shown in Fig. 3b. $\textit{V}{_\textrm{RF}}$ and $\textit{V}{_\textrm{RC}}$ ($\textit{V}{_\textrm{RF}}$ + $\textit{V}{_\textrm{RC}}$ = $\textit{V}{_\textrm{peak}}$) are the two inverted outputs in the ramp generator in Fig. 3b. $\textit{V}{_\textrm{peak}}$ represents the maximum voltage of the ramp, including the margin voltage needed for DCDS and the quantization range $\textit{V}{_\textrm{range}}$, $\textit{V}{_\textrm{rst}}$ is generally set to (($\textit{V}{_\textrm{peak}}$ + $\textit{V}{_\textrm{range}}$) / 2).

Fig. 3

a Structure diagram of the ramp generator and b Output timing diagram of the ramp generator

The simplified circuit structure of the TS-SS ADC of this design is shown in Fig. 4a, the working principle is as follows: during the reset phase, the comparator and precomparator are reset, and switch $\textit{S}{_\textrm{rst}}$ is turned off. As $\textit{V}{_\mathrm{in-}}$ starts to change, CLK[0] accesses the 0-bit of the counter to start counting. When $\textit{V}{_\mathrm{in-}}$ < $\textit{V}{_\mathrm{in+}}$, the comparator is flipped, the counter stops working, and the quantization result of the $\textit{V}{_\textrm{rst}}$ is $\textit{D}{_\textrm{out1}}$.

Fig. 4

a Simplified schematic of the proposed TS-SS ADC. b and c Schematic diagram of comparator operation for two different examples

During the signal phase, the complement (2${^N}$- $\textit{D}{_\textrm{out1}}$) of $\textit{D}{_\textrm{out1}}$ is obtained and the pixel signal $\Delta$ $\textit{V}{_\textrm{pixel}}$ is compared with the prejudgement signal $\Delta$ $\textit{V}{_\textrm{test}}$ ($\Delta$ $\textit{V}{_\textrm{test}}$ = $\textit{V}{_\textrm{rst}}$ - $\textit{V}{_\textrm{testn}}$).

If $\textit{V}{_\textrm{sig}}$ >$\textit{V}{_\textrm{testn}}$, switches $\textit{S}{_\textrm{G}}$ and $\textit{S}{_\textrm{H}}$ remain on, and SS ADC enters normal mode. The circuit structure is shown in Fig. 4b and the signal and timing are illustrated in Fig. 5a. The operation principle is the same as the conventional SS ADC, CLK[0] is connected to the 0-bit of the counter to start counting. When $\textit{V}{_\mathrm{in-}}$ < $\textit{V}{_\mathrm{in+}}$, the comparator is flipped, the counter stops working and the quantization result of the $\Delta$ $\textit{V}{_\textrm{pixel}}$ is $\textit{D}{_\textrm{out2}}$(a) - $\textit{D}{_\textrm{out1}}$, 2${^N}$ will not be credited to the final output. In normal mode, the clock step required for quantization is related to $\Delta$ $\textit{V}{_\textrm{test}}$. If $\Delta$ $\textit{V}{_\textrm{test}}$ >($\textit{V}{_\textrm{rst}}$ - $\textit{V}{_\textrm{peak}}$ / 2 = $\textit{V}{_\textrm{range}}$ / 2), and the clock step needs to be larger than (($\textit{V}{_\textrm{peak}}$ / $\textit{V}{_\textrm{range}}$) $\times$ 2${^{N-1}}$), and part of the pixel signal will not be quantized. Therefore, $\Delta$ $\textit{V}{_\textrm{test}}$ ${\le }$ ($\textit{V}{_\textrm{range}}$ / 2) must be satisfied. The larger the value of $\Delta$ $\textit{V}{_\textrm{test}}$, the more signals will enter normal mode. Since ramp signals require some design margin to perform DCDS operation, $\Delta$ $\textit{V}{_\textrm{test}}$ = ($\textit{V}{_\textrm{range}}$ / 2) can be selected so that as many signals as possible enter the normal mode.

If $\textit{V}{_\textrm{sig}}$ < $\textit{V}{_\textrm{testn}}$, switches $\textit{S}{_\textrm{G}}$ and $\textit{S}{_\textrm{H}}$ are off, and TS-SS ADC enters accelerated mode. The circuit structure is shown in Fig. 4c and the signal and timing are shown in Fig. 5b. When $\textit{V}{_\mathrm{in-}}$ starts to change, $\textit{V}{_\mathrm{in+}}$ also changes at the opposite rate, which corresponds to a comparison speed twice that of the normal mode. If the clock frequency of CLK[1] is equal to CLK[0], when CLK[1] is connected to the 1-bit of the counter to start counting, so the counter counts twice as fast as the normal mode. Due to the high photon shot noise of the high differential voltage pixel signals themselves, reducing the accuracy of the ADC in accelerated mode does not have a significant impact on linearity [2]. When $\textit{V}{_\mathrm{in-}}$ < $\textit{V}{_\mathrm{in+}}$, the comparator is flipped, the counter stops working and the quantization result of the $\Delta$ $\textit{V}{_\textrm{pixel}}$ is $\textit{D}{_\textrm{out2}}$(b) - $\textit{D}{_\textrm{out1}}$, 2${^N}$ will not be credited to the final output. The accelerated mode doubles the speed of quantizing pixel signals with high differential voltage, reducing the clock step required for the signal stage by (($\textit{V}{_\textrm{peak}}$ / $\textit{V}{_\textrm{range}}$) $\times$ 2${^{N-1}}$). In Fig. 5b, the gray line depicts the operation of a conventional SS ADC.

In the TS-SS ADC of this design, the accelerated mode changes the two inputs of the comparator by $\textit{V}{_\textrm{RF}}$ and $\textit{V}{_\textrm{RC}}$ instead of generating a $\textit{V}{_\textrm{2RF}}$ with twice the slope by digital DAC code for the following reasons:

The current steering DAC has a constant number of current sources and power consumption, $\textit{V}{_\textrm{RF}}$ and $\textit{V}{_\textrm{RC}}$ are voltage signals that are simultaneously generated and reversed by switch-controlled current sources. However, $\textit{V}{_\textrm{2RF}}$ with twice the slope would also require a current steering DAC structure to generate, which would result in more area and power consumption.

When pixel signals with high differential voltage are quantized by generating a two-fold sloped $\textit{V}{_\textrm{2RF}}$ with digital DAC code, the capacitive load driven by the $\textit{V}{_\textrm{RF}}$ will change due to the difference in the number of ADC columns going into normal and accelerated modes at different row cycles, so the row noise will be increased.

Fig. 5

a and b The timing diagrams of TS-SS ADC operation in normal mode and accelerated mode, respectively

2.3 Fixed Error and Linearity Error Analysis and Processing

Calibration is required for this quantization method because the signals at the two inputs of the comparator in Fig. 4c do not vary with exactly opposite slopes due to differences in capacitance driven by $\textit{V}{_\textrm{RC}}$ and $\textit{V}{_\textrm{RF}}$, as well as the presence of comparator parasitic capacitance.

Fig. 6

a and b Equivalent schematic diagram considering the comparator parasitic capacitance

Figure 6 shows the equivalent circuit takes into account the parasitic capacitance of the comparator. $\textit{C}{_\textrm{j1}}$ and $\textit{C}{_\textrm{j2}}$ represent the capacitors to ground for $\textit{V}{_\mathrm{in+}}$ and $\textit{V}{_\mathrm{in-}}$ at the comparator inputs, while $\textit{C}{_\textrm{j}}$ is the parasitic capacitance between the two comparator inputs. Based on the law of conservation of charge, the following two equations can be derived in Fig. 6a:

$$\begin{aligned}{} & {} (\Delta V_{in-}-\Delta V_{in+})C_{j}+(\Delta V_{in-}-\Delta V_{RF})C_{n} +\Delta V_{in-}C_{j2} =0 \end{aligned}$$

(1)

$$\begin{aligned}{} & {} (\Delta V_{in+}-\Delta V_{in-})C_{j}+\Delta V_{in+}C_{p}+\Delta V_{in+}C_{j1} =0 \end{aligned}$$

(2)

Combining Eqs. 1 and 2 and simplifying to obtain

$$\begin{aligned}&\Delta V_{in-}=\frac{\Delta V_{RF}C_{n}(C_{p}+C_{j1}+C_{j})}{[(C_{n}+C_{j2}+C_{j})(C_{p}+C_{j1}+C_{j})-C_{j}^{\text {2}}]} \end{aligned}$$

(3)

$$\begin{aligned}&\Delta V_{in+}=\frac{\Delta V_{RF}C_{n}C_{j}}{[(C_{n}+C_{j2}+C_{j})(C_{p}+C_{j1}+C_{j})-C_{j}^{\text {2}}]} \end{aligned}$$

(4)

Equation 5 is obtained by subtracting Eq. 4 from Eq. 3, which is given as

$$\begin{aligned} \Delta V_{act}(a)= \Delta V_{in-}- \Delta V_{in+} \end{aligned}$$

(5)

$\Delta$ $\textit{V}{_\textrm{act}}$(a) represents the equivalent change in ramp signal in Fig. 6a. Therefore, in normal mode, for any pixel signal $\Delta$ $\textit{V}{_\mathrm{pixel(sig1)}}$ = $\textit{V}{_\textrm{rst}}$ - $\textit{V}{_\textrm{sig1}}$ and $\Delta$ $\textit{V}{_\mathrm{pixel(sig2)}}$ = $\textit{V}{_\textrm{rst}}$ - $\textit{V}{_\textrm{sig2}}$, the quantization code values of the SS ADC are

$$\begin{aligned} D_{out}(a)&=\frac{(V_{rst}-V_{sig1})F_{CLK[0]}}{\Delta V_{act}(a)} \end{aligned}$$

(6)

$$\begin{aligned} \Delta D_{out}(a)&=\frac{(V_{sig2}-V_{sig1})F_{CLK[0]}}{\Delta V_{act}(a)} \end{aligned}$$

(7)

$\textit{F}{_\mathrm{CLK[0]}}$ is the frequency of the clock signals CLK[0]. Based on the law of conservation of charge, the following two equations can be derived in Fig. 6b:

$$\begin{aligned}{} & {} (\Delta V_{in-}-\Delta V_{in+})C_{j}+(\Delta V_{in-}-\Delta V_{RF})C_{n}+\Delta V_{in-}C_{j2} =0 \end{aligned}$$

(8)

$$\begin{aligned}{} & {} {Cr} =\frac{C_{p}C_{s}}{(C_{s}+C_{p})} \end{aligned}$$

(9)

$$\begin{aligned}{} & {} (\Delta V_{in+}-\Delta V_{in-})C_{j}+(\Delta V_{in+}-\Delta V_{RC})C_{r}+\Delta V_{in+}C_{j1} =0 \end{aligned}$$

(10)

Combining Eqs. 8, 9 and 10, simplifying to obtain

$$\begin{aligned} \Delta V_{in-}&=\frac{\Delta V_{RF}C_{n}(C_{r}+C_{j1}+C_{j})+\Delta V_{RC}C_{r}C_{j}}{[(C_{n}+C_{j2}+C_{j})(C_{r}+C_{j1}+C_{j})-C_{j}^{\text {2}}]} \end{aligned}$$

(11)

$$\begin{aligned} \Delta V_{in+}&=\frac{\Delta V_{RF}C_{n}C_{j}}{[(C_{n}+C_{j2}+C_{j})(C_{r}+C_{j1}+C_{j})-C_{j}^{\text {2}}]}\nonumber \\&\quad +\, (1+\frac{C_{j}^{\text {2}}}{[(C_{n}+C_{j2}+C_{j})(C_{r}+C_{j1}+C_{j})-C_{j}^{\text {2}}]}) \frac{\Delta V_{RC}C_{r}}{(C_{r}+C_{j1}+C_{j})} \end{aligned}$$

(12)

Equation 13 is obtained by subtracting Eq. 12 from 11, which is given as

$$\begin{aligned} \Delta V_{act}(b)= \Delta V_{in-}- \Delta V_{in+} \end{aligned}$$

(13)

$\Delta$ $\textit{V}{_\textrm{act}}$(b) represents the equivalent change in ramp signal in Fig. 6b. Therefore, in accelerated mode, for any pixel signal $\Delta$ $\textit{V}{_\mathrm{pixel(sig1)}}$ = $\textit{V}{_\textrm{rst}}$ - $\textit{V}{_\textrm{sig1}}$ and $\Delta$ $\textit{V}{_\mathrm{pixel(sig2)}}$ = $\textit{V}{_\textrm{rst}}$ - $\textit{V}{_\textrm{sig2}}$, the quantization code values of the SS ADC are

$$\begin{aligned} D_{out}(b)&=\frac{2(V_{peak}-V_{sig1}-V_{offset})F_{CLK[1]}}{\Delta V_{act}(b)}+t_{delay1}F_{CLK[1]}\nonumber \\&\quad -\,\left[ \frac{(V_{peak}-V_{rst}-V_{offset})F_{CLK[0]}}{\Delta V_{act}(a)}+t_{delay0}F_{CLK[0]}\right] \end{aligned}$$

(14)

$$\begin{aligned} \Delta D_{out}(b)&=\frac{2(V_{sig2}-V_{sig1})F_{CLK[1]}}{\Delta V_{act}(b)} \end{aligned}$$

(15)

$\textit{F}{_\mathrm{CLK[1]}}$ is the frequency of the clock signals CLK[1] before linearity calibration, $\textit{t}{_\textrm{delay0}}$ is the delay time for the comparator in the reset phase, and $\textit{t}{_\textrm{delay1}}$ is the delay time for the comparator in the signal phase in the accelerated mode. When Eqs. 7 and 15 are equal, the two modes have the same linearity and $\textit{F}{_\mathrm{CLK[1]}}$ can be expressed as:

$$\begin{aligned} F_{CLK[1]}=\frac{ \Delta V_{act}(b) F_{CLK[0]}}{2\Delta V_{act}(a)} \end{aligned}$$

(16)

To ensure the linearity of the ADC under different temperature and process corner conditions, the value of $\textit{F}{_\mathrm{CLK[1]}}$ needs to be determined after linearity calibration, as the value of the parasitic capacitance varies with temperature and process.

Fig. 7

Programmable capacitor array $\textit{C}{_\textrm{s}}$

It is therefore necessary to add a programmable capacitance array $\textit{C}{_\textrm{s}}$ to each ADC column, this allows for fine-tuning of the capacitance to compensate for variations caused by temperature and process changes, as shown in Fig. 7. The linearity and fixed error calibration block diagram and flowchart are shown in Fig. 8.

In the linearity calibration phase, the four-column linearity calibration Dummy SS ADCs are used to quantize the pixel signal $\Delta$ $\textit{V}{_\mathrm{pixel(rst)}}$ and $\Delta$ $\textit{V}{_\mathrm{pixel(testn)}}$ in normal mode and accelerated mode. The quantization results $\textit{D}{_\mathrm{out(1:4)}}$ are then input into the Linearity Calibration Module to obtain the calibration result:

$$\begin{aligned} D_{slope<12:0>}&=\frac{2(V_{rst}-V_{testn})F_{CLK[1]}}{\Delta V_{act}(b)}-\frac{(V_{rst}-V_{testn})F_{CLK[0]}}{\Delta V_{act}(a)}\nonumber \\&=(V_{rst}-V_{testn})\left( \frac{2F_{CLK[1]}}{\Delta V_{act}(b)}-\frac{F_{CLK[0]}}{\Delta V_{act}(a)}\right) \end{aligned}$$

(17)

The value $\textit{C}{_\textrm{s}}$ of the programmable capacitor array and the value of $\textit{F}{_\mathrm{CLK[1]}}$ are dynamically adjusted based on the $\textit{D}{_\mathrm{slope<12:0>}}$ results to ensure desirable linearity of the SS ADC at any process corners. $\textit{D}{_\mathrm{slope<12:0>}}$ are the result of a thirteen-bit binary code value.

If $\textit{D}{_\mathrm{slope<12>}}$ is "1" and the frequency of $\textit{F}{_\mathrm{CLK[1]}}$ needs to be increased.

If $\textit{D}{_\mathrm{slope<12>}}$ is "0" and $\textit{D}{_\mathrm{slope<11:5>}}$ are not all "0", then the frequency of $\textit{F}{_\mathrm{CLK[1]}}$ needs to be decreased.

If $\textit{D}{_\mathrm{slope<12:5>}}$ are "0", the values of $\textit{S}{_\mathrm{slope<2:0>}}$ can be automatically set according to the result of $\textit{D}{_\mathrm{slope<4:2>}}$, and the linearity calibration is completed. This dynamic adjustment of capacitor values and clock frequency ensures that the SS ADC maintains its desired linearity across different process corners and temperature variations.

Fig. 8

a and b The linearity and fixed error calibration block diagram and flowchart

Fig. 9

Timing diagram of TS-SS ADC operation after fixed error calibration

After linearity calibration, in accelerated mode, DCDS can only eliminate the effect of comparator mismatch, and the comparator delay will exist as an error. According to Eq. 14 this fixed error can be expressed as:

$$\begin{aligned} D_{fixed}&=\frac{2(V_{peak}-V_{sig1}-V_{offset})F_{CLK[S]}}{\Delta V_{act}(C_{s})}+t_{delay1}F_{CLK[S]}\nonumber \\&\quad -\,\left[ \frac{(V_{peak}-V_{rst}-V_{offset})F_{CLK[0]}}{\Delta V_{act}(a)}+t_{delay0}F_{CLK[0]}\right] \nonumber \\&=t_{delay1}F_{CLK[S]}-t_{delay0}F_{CLK[0]} \end{aligned}$$

(18)

$\textit{F}{_\mathrm{CLK[S]}}$ is the frequency of the clock signals CLK[1] after linearity calibration. $\Delta$ $\textit{V}{_\textrm{act}}$($\textit{C}{_\textrm{s}}$) represents the equivalent change in ramp signal after linearity calibration. Fixed errors can be calibrated by adjusting the starting value of the $\textit{V}{_\textrm{RC}}$ in the signal phase. The fixed error calibration Dummy SS ADC was used to quantize the $\textit{D}{_\textrm{fixed}}$ in accelerated mode and $\textit{D}{_\textrm{fixed}}$ is fed into the ramp generator to adjust the number of fixed error current sources in the signal phase to change the starting voltage value of the $\textit{V}{_\textrm{RC}}$, as shown in Fig. 9. The entire calibration circuit consists of a five-column Dummy SS ADC and a Linearity Calibration Module. The Linearity Calibration Module consists of a 13-bit full adder, a 4-bit bidirectional counter, and a number of logic modules, with a small circuit area. The TS-SS ADC performs only one linearity calibration in quantizing the pixel signals of all frames, and performs a fixed error calibration once per frame cycle, so the calibration circuit requires very low power consumption.

In the actual design, due to the mismatch of the precomparator, even if the precision of the $\Delta$ $\textit{V}{_\textrm{test}}$ voltage is very high and the noise value is very small, the precomparator will still make a misjudgment when the values of the pixel signals $\Delta$ $\textit{V}{_\textrm{pixel}}$ and $\Delta$ $\textit{V}{_\textrm{test}}$ are almost the same. However, after calibration is complete, any pixel signal $\Delta$ $\textit{V}{_\textrm{pixel}}$ can be quantized to approximately the same quantization code value in both normal and accelerated modes, so the accuracy and noise requirements of the $\Delta$ $\textit{V}{_\textrm{test}}$ voltage are not very high, and it can be generated by resistor voltage divider and switches. Here, the effect of KT/C noise on the signal $\Delta$ $\textit{V}{_\textrm{pixel}}$ is ignored, as stated in Ref. [13].

Fig. 10

20 Columns TS-SS ADC layout structure

3 Simulation Results

This 12-bit TS-SS ADC is designed in a 110 nm 1P4M CMOS technology. Figure 10 shows the layout of the 20 columns TS-SS ADC array, with each parallel SS ADC has a width of 5 µm and a height of 1200 µm. Compared to the conventional SS ADC structure, the column height is increased by approximately 250 µm and the area increased by 26%. Figure 11 shows the layout structure of the ramp generator, phase-locked loop (PLL) and four columns Dummy SS ADCs, with the ramp generator has a width of 1500 µm and a height of 760 µm, and the phase-locked loop has a width of 60 µm and a height of 640 µm. The added area of the five-column Dummy SS ADC, the linearity calibration module, and the phase-locked loop circuit PLL[1] circuits is small compared to the precomparator and programmable capacitor arrays required for each column of TS-SS ADCs, so the loss of area for the TS-SS ADCs in this design comes primarily from the precomparator arrays and programmable capacitor arrays, which is about 26%.

Fig. 11

Ramp generator and phase-locked loop layout structure

Fig. 12

DNL and INL of ADC

The average power consumption of the single-column SS ADC is 48.2 µW on a 3.3 V analog supply and a 1.5 V digital supply. It operates with a 320 MHz master clock, an 18.75 µs row cycle, and achieves a sampling rate of 53.3 Ks/S, and a quantization range of 1 V. DNL and INL are obtained through code density simulation using 30,720 points. Among these, 20,480 points are used for normal mode simulation, while 10,240 points are used for accelerated mode simulation. The simulation accuracy is set at 0.1 LSB, with an error margin of ± 0.05 LSB. In the accelerated mode, where the ADC precision is 11 bits and the counter has a counting weight value of 2, the loss of the lowest bit during DNL and INL simulations is disregarded. Figure 12 depicts the performance of the 12-bit TS-SS ADC, which showcases a DNL range of + 0.40/− 0.40 LSB and an INL range of + 2.30/− 0.3 LSB.

Table 1 Performance comparison

Table 1 presents parameters of the proposed SS ADC, including a FoM of 0.22 pJ/step and compares it with the conventional SS ADC and previous state-of-the-art column ADCs. The more common method of coarse and fine quantization is used in Ref. [16], but it requires the interplay of two ramp generators and capacitors, leading to increased circuit area and power consumption. In Ref. [13], a combination of a doubled output ramp generator and switched-capacitor circuit is employed to reduce the row cycle. The introduction of KT/C noise through the switch is negligible due to the presence of photon shot noise. In Ref. [5] a switch and reference voltage are utilized to divide the ramp into two upper and lower sections, saving the row cycle.

Table 2 Post-simulation results at different process corners

However, the presence of parasitic capacitance causes linearity mismatch in all the aforementioned papers. In this paper, the linearity of the two modes is analyzed and corrected using programmable capacitor arrays. Table 2 displays the post-simulation linearity of the accelerated and normal modes after calibration for different process corners and temperature, $\textit{D}{_\mathrm{slope<4:2>}}$ being the output of the calibrated circuit. Due to the larger parasitic capacitance in the actual layout, a smaller $\textit{F}{_\mathrm{CLK[S]}}$ is required to satisfy Eq. 16. As shown in the results of Table 2, the maximum linearity deviation is 0.12% for both modes at different process corners and temperatures.

Fig. 13

a and b The histograms of the Monte Carlo linearity deviation simulation of the TS-SS ADC in normal mode and accelerated mode, respectively

Fig. 14

Histogram of Monte Carlo fixed error simulation after DCDS in accelerated mode

The Monte Carlo linearity deviation simulation results are shown in Fig. 13, where the average linearity deviation in normal mode is 0.07% and the maximum linearity deviation is 0.12%, and the average linearity deviation in accelerated mode is 0.08% and the maximum linearity deviation is 0.21%. The Monte Carlo fixed error simulation results are shown in Fig. 14, where the data indicate that the mean fixed error $\textit{D}{_\mathrm{fixed(mean)}}$ is 62 Digital Number (DN) and the standard deviation $\delta {_\textrm{fixed}}$ is 0.86 DN. Indeed, the value of $\delta {_\textrm{fixed}}$ includes the mismatch of the comparator delay and the KT/C noise.

Table 3 Effect of photon shot noise on ADC performance at different conversion gains

According to the photon shot noise equation:

$$\begin{aligned} V_{shot}=CG\sqrt{\frac{\Delta V_{pixel}}{CG}} \end{aligned}$$

(19)

CG refers to the conversion gain of the sensor and $\textit{V}{_\textrm{shot}}$ denotes the photon shot noise of the differential pixel signal $\Delta$ $\textit{V}{_\textrm{pixel}}$. Table 3 provides the photon shot noise values for threshold signals with $\Delta$ $\textit{V}{_\textrm{pixel}}$ equal to 0.5 V at different conversion gains. It also illustrates the effect of these noise values on linearity. The data in Table 3 show that the linearity deviation brought by photon shot noise at different conversion gains is much larger than that brought by the TS-SS ADC in this design. In addition, in the accelerated mode, the $\delta {_\textrm{fixed}}$ is only 0.86 DN, which is much smaller than the effect caused by the photon shot noise, so this design can be applied to CIS.

4 Conclusion

This study proposes a novel approach for accelerating the quantization process in SS ADCs by leveraging differential topological characteristics. Firstly, the pixel signals are segmented using a precomparator to bring the large pixel signal into the accelerated mode, which reduces the row cycle of SS ADC. The value of the programmable capacitor array and the clock frequency can be adjusted with the Linearity Calibration Module so that the ADC maintains the same linearity in accelerated mode and normal mode. By adjusting the $\textit{V}{_\textrm{RC}}$ voltage in the signal phase, the problem of the DCDS function having a fixed error present in the acceleration mode has been solved. The effectiveness of the proposed method has been validated through rigorous simulations. Under Monte Carlo simulation, the average linearity deviation is 0.07%, with a maximum deviation of 0.21%. Under process corner post-simulation, the maximum linearity deviation is 0.12%. These results demonstrate the ability of the method to maintain high linearity across different process corners and temperatures. By incorporating the DCDS function, the row cycle at a frequency of 320 MHz can be reduced from 27.3 to 18.75 µs, resulting in a 31% reduction. Without the DCDS function, the row cycle can be reduced by 41.8%. Despite there is a 26% increase in circuit area for a single-column SS ADC, the quantization is faster and the FoM value of 0.22 pj/step outperforms the conventional SS ADC structure.